module top(
           input clk,
           input rst_n,
           input [1: 0] cnt_ctr,
           output reg [2: 0] cnt
       );

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			cnt <= 3'd0;
		else
			begin
				if (cnt_ctr == 2'b00 || cnt_ctr == 2'b11)
					cnt <= cnt;
				else if (cnt_ctr == 2'b01)
					cnt <= cnt + 1'b1;
				else if (cnt_ctr == 2'b10)
					cnt <= cnt - 1'b1;
			end
	end


endmodule
